1. Field of the Invention
The present invention relates to a semiconductor device with gate structures.
2. Description of the Background Art
For semiconductor devices with gate structures, one conventional method of element isolation is the well-known LOCOS (Local Oxidation of Silicon) technique. FIG. 13 is a cross-sectional view in schematic form illustrating a semiconductor device structure using the LOCOS technique. As shown in FIG. 13, a conventional semiconductor device includes a semiconductor substrate 100, a plurality of MOS transistors 120 (one of which is shown in the drawing) and an interlayer insulation film 102 formed of, for example, silicon oxide film, wherein LOCOS isolation films 101 provide isolation between each of the MOS transistors 120. In the surface of the semiconductor substrate 100, a P-type well region 190, for example, is formed. The MOS transistors 120 each have N-type source/drain regions 103, for example, spaced at predetermined intervals in the well region 190 and a gate structure 110 formed on the surface of the semiconductor substrate 100 sandwiched between the source/drain regions 103. The gate structure 110 includes a layered structure 200 in which a gate insulating film 104, a polysilicon film 106, a tungsten silicide film 107 and an insulation film 109 are stacked one above another in order from the semiconductor substrate 100 side, and sidewalls 105 formed on the side surfaces of the layered structure 200. The polysilicon film 106 and the tungsten silicide film 107 form a gate electrode 108, and the insulation film 109 is formed of, for example, silicon oxide film. The interlayer insulation film 102 is formed on the semiconductor substrate 100 to cover the gate structure 110 and the LOCOS isolation films 101.
In the above-described semiconductor device, a contact hole 111 is formed in the interlayer insulation film 102 for providing connection between a metal wiring layer (not shown) to be formed on the interlayer insulation film 102 and one of the source/drain regions 103 of the MOS transistor 120. More specifically, as shown in FIG. 13, using a patterned resist 112 formed on the interlayer insulation film 102 as a mask, the interlayer insulation film 102 is selectively dry etched to form the contact hole 111 which extends from the upper surface of the interlayer insulation film 102 to the semiconductor substrate 100. At this time, if the contact hole 111 is formed out of position, it may extend through the source/drain region 103 to the well region 190. In this condition, when the contact hole 111 is filled with a metal material and a metal wiring layer is formed on the interlayer insulation film 102 to be connected to the metal material, the metal wiring layer and the well region 190 will be connected to each other.
To prevent such a short between the metal wiring layer and the well region 190, a method has been adopted for forming, after the formation of the contact hole 111, a diffusion layer of the same conductivity type as the source/drain regions 103, in this case a P-type diffusion layer, in the well region 190 appearing in the bottom of the contact hole 111. This method is called an xe2x80x9cSAC (Self-Aligned Contact) implantation methodxe2x80x9d.
By the way, the aforementioned LOCOS technique could no longer conform to further requirement for device miniaturization from the market and thus, an STI (Shallow Trench Isolation) technique has been adopted as another method of element isolation. In the STI technique, however, even if the SAC implantation method is used to solve the aforementioned problem, it is difficult to form a homogenous P-type diffusion layer in the well region 190 appearing in the bottom of the contact hole 111, because of a steeply inclined trench formed in the semiconductor substrate 100 for element isolation. To cope with this problem, the method hitherto adopted is, as shown in FIG. 14, to form, after the formation of the MOS transistors 120, a stopper film 115 on the semiconductor substrate 100 to cover the surface of the gate structure 110 of the MOS transistor 120 and then to form the interlayer insulation film 102 on the stopper film 115. This stopper film 115 is formed of, for example, silicon nitride film and acts as an etch stop when a contact hole is formed in the interlayer insulation film 102. FIG. 14 and FIG. 15 which will be described later are cross-sectional views in schematic form illustrating a semiconductor device structure using STI isolation films 113 instead of the LOCOS isolation films 101 in the semiconductor device shown in FIG. 13.
As shown in FIG. 14, in order to provide connection between one of the source/drain regions 103 of the MOS transistor 102 and a metal wiring layer (not shown) formed in the upper part, the interlayer insulation film 102 is first selectively etched using the stopper film 115 as an etch stop to form a contact hole 114. Then, as shown in FIG. 15, the exposed stopper film 115 is selectively etched to form a contact hole 16, thereby completing the formation of a contact hole 111 which extends from the upper surface of the interlayer insulation film 102 to the semiconductor substrate 100. The process of forming the contact hole 111 extending from the upper surface of the interlayer insulation film 102 to the semiconductor substrate 100 in this way can be divided into two steps: the step of etching the interlayer insulation film 102 and the step of etching the stopper film 115, whereby the amount of the semiconductor substrate 100 to be etched by the formation of the contact hole 111 can be reduced. This prevents a short between the upper metal wiring layer and the well region 190.
To illustrate the above in a concrete form, the amount of overetch when forming a contact hole shall, for example, be 30% of the thickness of a film to be etched. For example, where the interlayer insulation film 102 has a thickness of 500 nm and no stopper film 115 is formed as in the semiconductor device shown in FIG. 13, the semiconductor substrate 100 will be etched to a depth of 150 nm from its upper surface, when the contact hole 111 is formed. In this case, the contact hole 111, if formed out of position, can extend to the well region 190.
In the semiconductor device with the stopper film 115 as shown in FIGS. 14 and 15, on the other hand, although the step of etching the stopper film 115 after etching of the interlayer insulation film 102 must additionally be provided, the thickness of the stopper film 115 is very small as compared with the interlayer insulation film 102 and thus, the amount of the semiconductor substrate 100 to be etched when the contact hole 111 is formed will be less than would be the case where the semiconductor device has no stopper film 115. To be more specific, where the stopper film 115 has a thickness of 50 nm, the semiconductor substrate 100 will be etched to a depth of only 15 nm from its upper surface when the contact hole 116 is formed. Thus, even if the contact hole 111 is formed out of position, it will not extend to the well region 190 as shown in FIG. 15.
Next, how, in the semiconductor device shown in FIGS. 14 and 15, the source/drain region 103 or the gate electrode 108 of the gate structure 110 is connected to the upper metal wiring layer formed in the interlayer insulation film 102 will be described in more detail with reference to FIGS. 16 to 20. FIGS. 16 to 20 are partial views of the semiconductor device shown in FIGS. 14 and 15.
First, as shown in FIG. 16, the source/drain regions 103 and the gate structure 110 of the MOS transistor 120 are formed and the stopper film 115 is formed on the semiconductor substrate 100 to cover the surface of the gate structure 110. Further, the interlayer insulation film 102 is formed on the stopper film 115 and the patterned resist 112 is formed on the interlayer insulation film 102. Using the resist 112 as a mask, the interlayer insulation film 102 is selectively etched to form the contact hole 114 which extends from the upper surface of the interlayer insulation film 102 to the stopper film 115. At this time, the stopper film 115 is used as an etch stop. Then, as shown in FIG. 17, the exposed stopper film 115 is selectively etched to form the contact hole 116, thereby completing the formation of the contact hole 111 which extends from the upper surface of the interlayer insulation film 102 to the semiconductor substrate 100.
The resist 112 used in the formation of the contact hole 111 is removed and, as shown in FIG. 18, a new resist 112 with a predetermined pattern is formed on the interlayer insulation film 102. Then, using the resist 112 as a mask, the interlayer insulation film 102, the stopper film 115 and the insulation film 109 of the gate structure 110 are selectively etched to form a contact hole 117 which extends from the upper surface of the interlayer insulation film 102 to the gate electrode 108 of the gate structure 110. At this time, etching is performed with no selectivity between each of the interlayer insulation film 102, the stopper film 115 and the insulation film 109 but with selectivity between the gate electrode 108 and each of the interlayer insulation film 102, the stopper film 115 and the insulation film 109. To be more specific, since, as above described, the interlayer insulation film 102 and the insulation film 109 are of silicon oxide film, the stopper film 115 is of silicon nitride film, and the upper part of the gate electrode 108 is of the tungsten silicide film 107, the contact hole 117 should be formed by etching with no selectivity between the silicon oxide film and the silicon nitride film but with selectivity between the tungsten silicide film 107 and each of the silicon oxide film and the silicon nitride film.
Then, as shown in FIG. 19, the resist 112 is removed, and metal materials 118 and 121 are buried respectively in the contact holes 111 and 117. After that, on the interlayer insulation film 102, a first metal wiring layer 119 is formed to be connected to the metal material 118 and a first metal wiring layer 122 is formed to be connected to the metal material 121. This provides connection between the source/drain regions 103 and the upper first metal wiring layer 119 and between the gate electrode 108 of the gate structure 110 and the upper first metal wiring layer 122. Then, as shown in FIG. 20, second metal wiring layers 127 and 128 formed in the upper reaches of the first metal wiring layers 119 and 122 are connected respectively to the first metal wiring layers 119 and 122. More specifically, an interlayer insulation film 129 is formed on the interlayer insulation film 102 to cover the first metal wiring layers 119 and 122. The interlayer insulation film 129 is then selectively etched using a resist with a predetermined pattern as a mask, thereby to form a contact hole 123 which extends from the upper surface of the interlayer insulation film 129 to the first metal wiring layer 119 and a contact hole 124 which extends from the upper surface of the interlayer insulation film 129 to the first metal wiring layer 122. Further, metal materials 125 and 126 are buried respectively in the contact holes 123 and 124. Then, by forming the second metal wiring layers 127 and 128 on the interlayer insulation film 129 to be connected to the metal materials 125 and 126, respectively, connection is provided between the second metal wiring layer 127 and the first metal wiring layer 119 and between the second metal wiring layer 128 and the first metal wiring layer 122. This results in connection between the source/drain region 103 and the second metal wiring layer 127 and between the gate electrode 108 of the gate structure 110 and the second metal wiring layer 128.
Here, as a means for improving efficiency in semiconductor device manufacturing, it is generally required to reduce the number of masking processes. In the aforementioned conventional semiconductor device manufacturing process illustrated in FIGS. 16 to 20, in order to reduce masking processes, it is contemplated, for example, to form the contact holes 111 and 117 at the same time. However, simultaneous proper formation of the contact holes 111 and 117 is difficult for the following reason. If the contact holes 111 and 117 are simultaneously formed by the etching used for forming the contact hole 117 in accordance with a distance (hereinafter referred to as a xe2x80x9cdistance xxe2x80x9d) from the upper surface of the interlayer insulation film 102 to the surface of the semiconductor substrate 100, even if the etching has selectivity to the tungsten silicide film 107 of the gate electrode 108, the contact hole 117 may extend through the tungsten silicide film 107 because of a difference between the distance x and a distance (hereinafter referred to as a xe2x80x9cdistance yxe2x80x9d) from the upper surface of the interlayer insulation film 102 to the upper surface of the gate electrode 108 of the gate structure 110. Or if the contact holes 111 and 117 are simultaneously formed in accordance with the distance y by the etching used for forming the contact hole 117, the formation of the contact hole 111 extending to the semiconductor substrate 100 may not be completed.
Further, even when the interlayer insulation film 102 is first etched to the stopper film 115 by using the stopper film 115 as an etch stop and then the remaining portions are etched at the same time, it is difficult to simultaneously form the contact holes 111 and 117 properly. More specifically, while the insulation film 109 is formed between the stopper film 115 on the gate structure 110 and the gate electrode 108, between the stopper film 115 on the source/drain regions 103 and the semiconductor substrate 100 is an oxide film (not shown) which could not completely be removed during process and which is extremely thin as compared with the insulation film 109. Thus, even when the interlayer insulation film 102 is first etched to the stopper film 115 and then the remaining portions are simultaneously etched, because of different layer structures of the remaining parts, it will be difficult to simultaneously form the contact holes 111 and 117 properly. As above described, the conventional semiconductor device manufacturing method illustrated in FIGS. 16 to 20 has difficulty in reducing the number of masking processes.
An object of the present invention is to provide a semiconductor device which is capable of reducing the number of masking processes in forming contact holes.
The semiconductor device according to the present invention includes a semiconductor substrate, a gate structure, an active region, a stopper film, a first interlayer insulation film, a first contact hole, a metal material, a metal wiring layer, a second interlayer insulation film, a second contact hole, and a third contact hole. The gate structure is selectively formed on the semiconductor substrate and has a layered structure in which a gate electrode and an insulation film are stacked one above the other in order from the semiconductor substrate side. The active region is formed in a main surface of the semiconductor substrate. The stopper film covers a whole surface of the gate structure and is formed on the active region. The first interlayer insulation film is formed on the stopper film. The first contact hole extends from an upper surface of the first interlayer insulation film to the active region. The metal material is buried in the first contact hole. The metal wiring layer is formed on the first interlayer insulation film to be connected to the metal material. The second interlayer insulation film is formed on the first interlayer insulation film to cover the metal wiring layer. The second contact hole extends from an upper surface of the second interlayer insulation film through the first interlayer insulation film, the stopper film and the insulation film to the gate electrode of the gate structure. The third contact hole extends from the upper surface of the second interlayer insulation film to the metal wiring layer and is shallower than the second contact hole. An etch rate of a film in forming the second and third contact holes is larger than that of the metal wiring layer.
In this semiconductor device, the second contact hole is provided which extends from the upper surface of the second interlayer insulation film to the gate electrode of the gate structure. This second contact hole can be formed at the same time as the third contact hole extending from the upper surface of the second interlayer insulation film to the metal wiring layer. Accordingly, a smaller number of masking processes is required when manufacturing the semiconductor device according to the second aspect than would be required when manufacturing a semiconductor device which includes, instead of the second contact hole, contact holes formed independently in the first and second interlayer insulation films.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.